Physical verification is the process of checking, using electronic design automation (EDA) software tools, whether an integrated circuit (IC) layout design meets certain criteria. IC layout is the representation of the IC in terms of planar geometric shapes which correspond to the patterns of metal, oxide and/or semiconductor layers that make up the components of the integrated circuit. Within the physical verification process, a layout generated for an IC is typically required to pass a series of checks. Such checks typically include design rule checking (DRC), layout versus schematic (LVS) checks, etc.
DRC is used to determine whether the physical layout of a particular IC layout satisfies a series of recommended parameters called design rules. The design rules are a series of parameters provided by a semiconductor manufacturer that enable the designer to verify the correctness of a mask set in terms of manufacturing process constraints, etc. As such, design rules are typically specific to a particular semiconductor manufacturing process. For example, a design rule set may specify certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes. Examples of some basic design rules include a minimum width of any shape in the IC design, a minimum distance between two adjacent objects, etc.
DRC software usually takes as an input a file containing IC layout information, for example in the GDSII standard format, and a list of rules specific to the semiconductor manufacturing process. GDSII (Graphic Design System II) is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form. The data can be used to reconstruct all or part of the artwork to be used in sharing layouts, transferring artwork between different tools, or creating photomasks. The DRC software then checks that the design rules have been complied with, and produces a report of design rule violations that the designer may or may not choose to correct. Such design rule checking does not validate the design, but checks that certain design rules intended to ensure a high overall yield and reliability for the design are complied with.
LVS is used to determine whether a particular IC layout corresponds to the original schematic or circuit diagram for the IC design. LVS checking typically involves three steps:                1. Extraction: the LVS software takes as an input a file containing IC layout information, for example in the GDSII standard format, and performs area based logic operations to identify IC components and connections within the IC layout;        2. Reduction: the LVS software combines the extracted components into series and parallel combinations, if possible, and generates a netlist representation of the IC layout (‘layout netlist’)—a similar reduction into series and parallel combinations is performed on the source schematic or circuit diagram netlist for the IC design;        3. Comparison: the LVS software then compares the layout netlist and (reduced) schematic/circuit diagram netlist to see if the two netlists ‘match’.        
Other verification checks may also be performed on an IC layout. For example, for power semiconductor devices, the Safe Operating Area (SOA) is defined as the voltage and current conditions over which the device can be expected to operate without self-damage. Accordingly, it is known to perform SOA reliability checks on IC layout designs for such devices whereby SOA rules may be implemented in a similar manner to the design rule set in order to ensure a high overall reliability for the design in relation to desired SOA conditions.
A problem with such conventional verification checks is that they do not take into consideration potential effects of the relative position of individual components and connections relative to one another, and other layout dependent factors. For example, using current physical and SOA verification techniques, design rules and SOA rules are currently limited to comparing measured values taken from the IC layout information with design and SOA rule values calculated using component specific parameters defined within schematic data for individual components and/or their respective device model, such as the length and width of a component's physical ‘shape’ within an IC layer, and/or general parameters applicable to the entire IC design, such as a minimum width of any shape in the IC design, a minimum distance between two adjacent objects, etc.
However, the performance of individual components is not solely dependent on such component specific parameters, which relate to individual components in isolation, and/or on overly generic parameters applicable to the entire IC layout. As a result, conventional design rules tend to be overly restrictive, often resulting in overly cautious designs of the IC layout, and thus in sub-optimal layout designs.